The isolation of semiconductor devices fabricated on a wafer or substrate has traditionally been performed using local oxidation of substrate ("LOCOS") isolation techniques in both bulk silicon substrate applications and silicon-on-insulator ("SOI") substrate applications. More recently, device isolation is being performed using trench isolation such as shallow trench isolation in bulk silicon substrate applications and mesa isolation in SOI substrate applications. Trench isolation provides advantages in both bulk substrate applications and SOI substrate applications. Trench isolation appears to provide even greater advantages in SOI substrate applications due to the ability to achieve isolation with a relatively shallow trench.
Although trench isolation techniques provide significant advantages, along with these advantages come certain problems and disadvantages. Specifically, when attempting to isolate an area, such as a gate junction or channel in a field-effect transistor or metal-oxide semiconductor field-effect transistor ("MOSFET"), from other devices or regions using trench isolation technology, the threshold voltage ("V.sub.t ") is lowered due to the presence of a parasitic transistor at the edge or corner where a trench wall meets the edge of the transistor. Furthermore, the gate oxide integrity ("GOI") is often degraded. These problems, present in both bulk silicon substrate applications and SOI substrate applications, are caused by the compressive thinning of the gate oxide and the two-dimensional field-effects at the top corner or edge where the trench wall meets the edge of the transistor. The lower threshold voltage V.sub.t of the parasitic transistor is caused by the sharp corner or edge which allows leakage currents to flow before the threshold voltage V.sub.t of the main transistor is reached. The sharp corner or edge has a relatively small radius of curvature which decreases the threshold voltage V.sub.t of the parasitic transistor. The GOI is compromised because of the compressive thinning of the gate oxide that forms around the top corner or edge where the trench wall meets the edge of the transistor or MOSFET. This thinning region has a lower breakdown voltage which decreases overall device reliability.
The presence of the parasitic transistor with the low threshold voltage V.sub.t produces excessive or higher off-state leakage currents which substantially increases overall power consumption. The off-state leakage currents also result in excess heat generation and cause problems related to the dissipation of this excess heat. GOI degradation impairs and reduces overall system or chip reliability.